Advanced semiconductor chips, such as high performance microprocessor, microcontroller and communication chips, require high speed interconnect structures between individual semiconductor devices which are used to perform various functions such as logical operations, storing and retrieving data, providing control signals and the like. With the progress in the semiconductor device technology leading to ultra large scale integration, the overall speed of operation of the advanced semiconductor chips is approaching a limit due to signal propagation delay in interconnection wires, which are employed as the high speed interconnect structures, between the individual semiconductor devices on the same advanced semiconductor chip.
The signal propagation delay in an interconnect structure is dependent on an RC product of the interconnect structure, where R denotes the resistance of the interconnect wires and C which the interconnect wires are embedded. Use of copper instead of aluminum as the interconnect wiring material has allowed reduction of the resistance contribution to the RC product. Current focus in microelectronics industry is on reducing the interconnect capacitance by employing low dielectric constant (low k) dielectric materials in the interconnect structure of the advanced semiconductor chips, which typically contain a multilayered interconnect structure.
One prior art method of forming an interconnect structure with small feature sizes is the dual damascene (DD) process described, for example, in W. Cote et al, “Non-Poisoning Dual Damascene Patterning Scheme for Low-k and Ultra Low-k BEOL,” Proceedings of 2006 Advanced Metallization Conference, pp. 43-44, October (2006). In general, a back end of the line (BEOL) interconnect structure comprises two types of features: metal lines that extend along in a horizontal direction across a semiconductor chip, and metal vias which extend vertically to connect metal lines at different levels of the BEOL interconnect structure. In the DD process, metal lines at a same level and metal vias located directly below the level of the metal lines are formed at the same processing step by filling line trenches formed at the same level and via holes formed directly below the level of the line trenches with metal, followed by planarization of the metal.
The level of the metal vias is referred to as a via level, which also comprises a via level dielectric material as well as the metal vias. The level of the metal lines is referred to as a line level, which also comprises a line level dielectric material as well as the metal lines. Historically, both the via level dielectric material and the line level dielectric material comprise an inorganic glass such as undoped silicate glass (USG) or a fluorosilicate glass (FSG), which is typically deposited by plasma enhanced chemical vapor deposition (PECVD). Recently, low dielectric constant (low k) organosilicate films comprising silicon, carbon, oxygen and hydrogen have been introduced as the via level dielectric material and the line level dielectric material to enable reduction in interconnect capacitance, and consequently, reduction in signal propagation delays in the advanced semiconductor chips.
A dual damascene process sequence is commonly employed to fabricate a back end of the line copper interconnect structures for the advanced semiconductor chips. One of the commonly used back end of the line integration scheme that employs the dual damascene process sequence is known as a “via first” integration scheme, in which via holes are formed first followed by formation of line trenches. Subsequently, metal vias are formed in the via holes and metal liners are formed in the line trenches during the same processing step that typically employs metal plating and chemical mechanical polishing (CMP).
An exemplary prior art via first integration scheme is schematically illustrated in FIGS. 1A-1I. Referring to FIG. 1A, a substrate 1000 containing at least one semiconductor device (not shown) is provided. The substrate 1000 may, or may not, comprise at least one interconnect wiring (not shown). A first intermetal dielectric (IMD) layer 1100 is formed on the substrate 1000 with a first level damascene metal line 1200 embedded therein. The first level damascene metal line 1200 typically comprises a first conductive diffusion barrier/adhesion layer 1210, which is often referred to as a barrier metal liner. The first level damascene metal line 1200 further comprises a first level metal line 1220, which typically comprises copper. A diffusion barrier dielectric layer 1230, which typically comprises silicon nitride, silicon carbide or silicon carbonitride, is deposited atop the embedded first level damascene metal line 1200 and the first IMD layer 1100.
A second intermetal dielectric (IMD) layer 1300 is then applied on top of the diffusion barrier dielectric layer 1230. The total thickness of the second IMD layer 1300 and the diffusion barrier dielectric layer 1230 is nominally equal to the sum of a target of a dual damascene line and a target height of a dual damascene via. As mentioned above, the first IMD layer 1100 and/or the second IMD layer 1300 typically comprise a low k (k<3.0) organosilicate dielectric material or an ultra low k (k<2.5) organosilicate dielectric material in the advanced semiconductor chips. The porosity level of the low k or ultra low k organosilicate dielectric materials increases as the dielectric constant k decreases.
A hard mask layer 1400 is deposited on top of the second IMD layer 1300 to protect the top surfaces of the IMD layer 1300 during subsequent lithography and etch processes. Typically the hard mask layer 1400 is an oxide layer formed by plasma enhanced chemical vapor deposition (PECVD) employing precursors such as silane, oxygen, or TEOS. Alternately, the hard mask layer 1400 may comprise silicon, carbon, oxygen, hydrogen (referred to as SiCOH), and optionally nitrogen, and is deposited employing precursors containing oxygen, silane, methylated silane, octamethyltetrasiloxane, and the like.
A first antireflective coating (ARC) layer 1450 is then applied to mitigate reflections from the first and second IMD layers (1100, 1300) during lithography. The first ARC layer 1450 typically comprises an optically absorptive organic material having a specific refractive index and a thickness tuned for this function. A first photoresist 1500 is applied and patterned by photolithography to form a via hole pattern 1510 within the layer of the first photoresist 1500 on top of the first ARC layer 1450.
Referring to FIG. 1B, the via hole pattern 1510 is sequentially transferred into the first ARC layer 1450, the hard mask layer 1400 and the second IMD layer 1300 using a reactive ion etch (RIE) process to produce a via hole 1600. A top surface of the diffusion barrier dielectric layer 1230 is exposed after the reactive ion etch.
Referring to FIG. 1C, remaining portions of the first photoresist 1500 and the first ARC layer 1450 are then stripped, for example, by a plasma ashing process. The strip process can be performed in the same process chamber as, or in a different process chamber from, the process chamber used for the RIE process of FIG. 1B. Typically, stripping damage is sustained by the second IMD layer 1300 during the strip process.
Referring to FIG. 1D, a disposable via fill material is applied over the hard mask layer 1400 to form a disposable via fill layer 2100, which fills the via hole 1600 and provides a substantially planar overfill over the hard mask layer 1400. The disposable via fill material may comprise an organic material that is capable of a gap fill of the via hole 1600. Preferably, the disposable via fill layer 2100 is self-planarizing. Non-limiting examples of the disposable via fill material include NFC1400™ produced by JSR Corporations, Japan, and Accuflow™ produced by Honeywell Microelectronic Materials™, Sunnyvale, Calif.
Typically, the disposable via fill material is an organic material having a low molecular weight, i.e., having a molecular weight less than 100,000, and more preferably, having a molecular weight less than 30,000. The disposable via fill material has a gap fill property that enables filling the via hole 1600 with the disposable via fill material. The disposable via fill material also meets etch rate contrast requirements relative to the organosilicate dielectric material of the second ILD layer 1300.
A low temperature oxide (LTO) layer 2200 is deposited by a suitable deposition method such as plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), or spin coating. Typically, a deposition temperature below 250° C. is desirable for the deposition of the LTO layer 2200. The disposable via fill material 2100 is thermomechanically stable during the deposition of the LTO layer 2200, and has a sufficient etch rate differential during a subsequent reactive ion etch (RIE) relative to the second IMD 1300 layer, which typically comprises an organosilicate glass. As will be seen subsequently, the disposable via fill layer 2100 provides the function of an RIE etch mask in the patterning of line trenches in the second IMD layer 1300.
A second antireflective coating (ARC) layer 2300 and a second photoresist 2400 are thereafter applied on top of the LTO layer 2200. The second photoresist 2400 is then patterned to form a line trench pattern 2500 within the layer of the second photoresist 2400 on top of the second ARC layer 2300.
Referring to FIG. 1E, the line trench pattern 2500 in the second photoresist 2400 is transferred by a RIE process into the second ARC layer 2300, the LTO layer 2200, and the disposable via fill layer 2100. During the RIE process, the second photoresist 2400 and the second ARC layer 2300 are typically consumed as they are etched concurrently with the etching of the exposed portions of the disposable via fill layer 2100. At the moment top surfaces of the hard mask layer 1400 are exposed, the remaining portions of the LTO layer 2200 constitutes a patterned LTO layer 2210, and remaining portions of the disposable via fill layer 2100 comprises a patterned disposable material layer 2110 and a via plug 2600.
Referring to FIG. 1F, as the RIE process continues, the patterned LTO layer 2210 is typically completely consumed during the etching of the hard mask layer 1400 and the early stage of etching of the second IMD layer 1300. The remaining portion of the via plug 2600 constitutes a disposable via fill plug 2710. The pattern transfer through the RIE process continues further into the second IMD layer 1300 employing the patterned disposable material layer 2110 as an etch mask to form a line trench 2800. The etch depth of line trench 2800 in the second IMD layer 1300 is determined based on the target height of a metal line in a completed dual damascene structure.
Referring to FIG. 1G, the patterned disposable material layer 2110 and disposable via fill plug 2710, both of which comprise the material of the disposable via fill material of the disposable via fill layer 2100 in FIG. 1D, are subsequently stripped using a plasma strip process. This plasma strip process induces most of the plasma damage in the second IMD layer 1300 since all the side walls of the line trench and the via opening are exposed to a strip plasma that needs to be aggressive enough to remove all of the patterned disposable material layer 2110 and the disposable via fill plug 2710. Any residual material from the disposable via fill plug 2710 left over in the via hole prevents or degrades a metal to metal contact between a fill metal to be formed at the via opening and the first level metal line 1220 when the dual damascene structure is metallized. Absence or degradation of the metal to metal contact results in low electrical yield.
Thus an optimally aggressive strip is normally employed in the plasma strip process. As a result, portions of the second IMD layer 1300 underneath the exposed sidewalls and horizontal surfaces of the second IMD layer 1300 are plasma damaged and chemically modified (loss of carbon content) to a certain depth to form a plasma damaged IMD region 3050. A first width W′ of the line trench denotes the horizontal distance between the exposed sidewall surfaces of the plasma damaged IMD region 3050 in the line trench.
Referring to FIG. 1H, the diffusion barrier dielectric layer 1230 is etched by a RIE to open a contact hole to the first level damascene metal line 1200 underneath. A via cavity 3150 is formed between the line trench 2800 and the first level damascene metal line 1200. This processing step is often performed in a process chamber in the same tool cluster as the tool cluster containing the RIE chamber used for patterning of the metal line as shown in FIG. 1F. Further, the RIE chamber and the strip chambers are often part of a single tool cluster with a provision for transferring a substrate from one to the other without exposure to ambient air.
After completion of the plasma strip processing, a wet clean may optionally be employed to remove any residual material left in the via hole. The residual material may contain silicon since the residual material may be generated from reaction products of the second IMD layer 1300 and/or the hard mask layer 1400 with plasma gas species, or the residual material may comprise a resputtered silicon containing material from the second IMD layer 1300 and/or the hard mask layer 1400. A wet clean including a dilute hydrofluoric acid (DHF) treatment is often employed to effect the cleaning of the residual material. While being effective for silicon containing residual materials, the wet clean also tends to dissolve all or at least a large portion of the plasma damaged IMD region 3050. This results in an increase in the width of the line trench. A second width W″ of the line trench denotes the horizontal distance between the exposed sidewall surfaces of the second IMD region 1300 in the line trench.
The second width W″ is greater than the first width W′ since the line trench 2800 widens during the wet clean. Depending on the extent of the plasma damaged IMD region 3050, the incremental change from the first width W′ to the second width W″ may be a significant fraction of the first width W′. To compensate for this incremental change, the corresponding line width in the line trench pattern 2500 in the second photoresist 2400 in FIG. 1D needs to be printed smaller than the second width by an amount equivalent to the sum of the etch bias during the transfer of the line trench pattern 2500 into the second IMD layer 1300 and the incremental change from the first width W′ to the second width W″. This lithographic constraint becomes a particularly challenging problem in the construction of high performance, high density metal interconnects in which fine line widths are required and porous ultra low dielectric constant IMD materials are employed since increased porosity renders the ultra low dielectric constant IMD materials prone to significant plasma damage, and consequently, a significant incremental change from the first width W′ to the second width W″.
Referring to FIG. 1I, the via cavity 3150 and the line trench 2800, which collectively constitute a dual damascene cavity (2800, 3150), are thereafter metallized, i.e., filled with metal by a plating process, followed by planarization, for example, by chemical mechanical polishing (CMP) to form a dual damascene metal interconnect structure 3200 which comprises a second conductive diffusion barrier/adhesion layer 3210 and second level integrated metal line and via 3220 which typically comprise copper. The processing steps of 1A-1I may be repeated to construct a multi-level dual damascene metal interconnect structure (not shown).
Alternate integration schemes may also be used for constructing a dual damascene metal interconnect structure in which a line trench is formed prior to formation of a via hole. While the sequence of process flow of the alternate integration schemes is different from the process flow of the via first integration scheme described above, the salient concerns regarding the exposure of the low k or ultra low k IMD material to plasma damage and widening of the line trench during a wet clean are also applicable to such alternate integration schemes.
In order to lower the interconnect capacitance, it is necessary to use lower k dielectrics such as PECVD or spin-on organosilicates which have k values in the range from about 2.7 to about 3.0 instead of a PECVD silicon dioxide based dielectrics having k values from about 3.6 to about 4.1. Structurally, the organosilicates have a silica-like backbone with alkyl or aryl groups attached directly to the Si atoms in the network. Their elemental compositions generally comprise Si, C, O, and H in various ratios. The C and H are most often present in the form of methyl groups (—CH3). The primary function of the methyl groups is to create a free volume in, and reduce the polarizability of, layers of the organosilicates that are formed in a metal interconnect structure. A secondary function of the methyl groups is to add hydrophobicity to the organosilicates. The k value can be further reduced to 2.2 (ultra low k) and even below 2.0 (extreme low k) by introduction of porosity in the layers of the organosilicates. For the purpose of brevity, the ultra low k and extreme low k materials are herein collectively referred to as very low k materials.
Although a tunable range of k values is possible with this set of very low k materials, there are several difficulties in integrating these materials with copper interconnects in a dual damascene process sequence described above or by any other variation of the dual damascene process sequence. The main difficulty is that the organosilicates are very sensitive to a plasma exposure because of the relative ease of oxidation or cleavage of the Si-organic group linkage (for example, Si-methyl) which results in formation of silanol (Si—OH) groups in the film through a reaction with moisture in the ambient atmosphere. Silanols further absorb moisture and hence increase the dielectric constant and the dielectric loss factor of the film significantly, thus negating the performance benefits expected from the very low k material. Silanols also increase the electrical leakage in the very low k material, and thus create a potentially unreliable interconnect structure. Since reactive ion etch and plasma etch are key steps required in the formation of the line trench and via openings in the dual damascene process sequence and in the removal of photoresists used in patterning the very low k materials as described above, it is very difficult, if not impossible, to avoid plasma damage of the very low k material during a dual damascene process sequence known in the art.
While several attempts have been made to minimize the loss of hydrophobicity in the low k films using non-oxidizing resist strip plasmas consisting of some or all of He, H2, N2, CO etc., none of these plasma chemistries known in the art succeed in completely preventing the loss of hydrophobicity of the very low k materials. This is especially the case for porous low k materials which have a very large surface area, and consequently are susceptible to damage during the resist strip processes. Further, use of less damaging strip processes often limits the efficacy with which photoresist and a disposable via fill plug are removed. Reduction in the efficacy of the photoresist and the disposable via fill plug may in turn result in unwanted organic residues in the metal interconnect structure, which are detrimental to effecting good metal fills and metal to metal contacts in a multilevel metal interconnect structure. Thus the use of such mild stripping plasma processes tends to limit the overall process window of the DD process and yield.
Another method of circumventing the problem of plasma damage caused by a plasma strip process is use of fluorinated or non-fluorinated organic polymer based low k materials such as Dow Chemical's SiLK™ dielectric, Honeywell's Flare™, polyimides, benzocyclobutene, polybenzoxazoles, aromatic thermoset polymers based on polyphenylene ethers; chemical vapor deposited polymers such as poly(p-xylylene) which are not susceptible to damage during conventional plasma strip processes. However, these materials do not possess the other properties required of a low k dielectric material such as a low thermal expansion, high hardness, and small pore sizes provided by porous organosilicate materials. Hence, use of the fluorinated or non-fluorinated organic polymer based low k materials causes reliability concerns.
Methods of partially repairing and restoring properties of the plasma damaged organosilicate IMD layer up to some degree are known in the prior art. The most common of these methods is known as a silylation process, wherein the plasma damaged organosilicate IMD layer is exposed to suitable reaction agents known as silylation agents with a structural formula Xn—Si—Rm, where m+n=4, which react with the silanols in the plasma damaged organosilicate IMD layer. The reaction removes hydrogen from the —OH groups in the silanols forming a volatile product that can be removed, while leaving a Si—O—Si—R moiety in the plasma damaged organosilicate IMD layer. The resulting structure is hydrophobic due to the organic group R, and if the replacement is complete, that is, if all silanol groups are reacted with the agent, the dielectric properties of the plasma damaged organosilicate IMD layer can be partially restored. Examples of silylation agents include but not limited to mono-, di- or trichloro silane, mono-, di- or tri-ethoxy or methoxy silane, bis(dimethyl amino)dimethyl silane and the like. U.S. Pat. No. 7,179,758 to Chakrapani et al. discloses several preferred silylation agents and silylation reaction methodologies, and is herein incorporated by reference.
One limitation of these repair methods is the degree to which the damage can be remediated. The effectiveness of the repair could be affected by the relative size and reactivity of the silylation agent molecules and pore diameters in the ultra low k IMD layer as well as possible steric hindrance generated when one of the Si—OH sites has reacted with the agent molecule, thus restricting access for further reaction with a neighboring silanol site. As porosity levels are increased to lower the dielectric constant of the ultra low k IMD layer, the level of plasma damage tends to increase, and concomitantly as pore sizes are reduced to improve the properties of the ultra low k IMD layer, the ability to repair the damage after it has already been generated becomes more difficult.
In view of the above, there exists a need for a method for minimizing or preventing the plasma damage inflicted upon the ultra low k IMD layer during formation of a dual damascene metal interconnect structure, while retaining the capability to employ a plasma strip process required to enable full removal of photoresist and a disposable via fill plug used in the dual damascene process sequence.
Further, there exists a need for a method of forming a dual damascene metal interconnect structure in which the line width of a metal line is not significantly increased from the line width of a lithographic pattern used to define the same.
In addition, there exists a need for a method of forming a dual damascene metal interconnect structure in which a more manufacturable lithographic process window may be employed for forming fine metal lines required in high density BEOL metal interconnect structures.